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FEATURES 50 Mbps to 3.3 Gbps Operation Single 3.3 V Operation Typical Rise/Fall Time 80 ps Bias Current Range 2 mA to 100 mA Modulation Current Range 5 mA to 80 mA Monitor Photodiode Current 50 A to 1200 A Dual MPD Functionality for DWDM 50 mA Supply Current at 3.3 V Closed-Loop Control of Power and Extinction Ratio Full Current Parameter Monitoring Laser Fail and Laser Degrade Alarms Automatic Laser Shutdown, ALS Optional Clocked Data Supports FEC Rates 48-Lead (7 mm 7 mm) LFCSP Package 32-Lead (5 mm 5 mm) LFCSP Package Available in Die Form
3 V Dual-Loop 50 Mbps to 3.3 Gbps Laser Diode Driver ADN2847
APPLICATIONS SONET OC-1/3/12/48 SDH STM-0/1/4/16 Fibre Channel Gigabit Ethernet DWDM Dual MPD Wavelength Control GENERAL DESCRIPTION
The ADN2847 uses a unique control algorithm to control both average power and extinction ratio of the laser diode, LD, after initial factory setup. External component count and PCB area are low as both power and extinction ratio control are fully integrated. Programmable alarms are provided for laser fail (end of life) and laser degrade (impending fail). Optional dual MPD current monitoring is designed into the ADN2847 specifically for DWDM wavelength control.
FUNCTIONAL BLOCK DIAGRAM
IMPDMON2 DEGRADE IMPDMON
IMMON
IBMON
VCC
CLKSEL
GND
FAIL
ALS
VCC
IMODN
VCC LD IMODP
VCC MPD IMPD IMOD IMPD2 CONTROL GND PSET IBIAS GND ERSET
DATAP DATAN CLKP CLKN IBIAS ASET
ADN2847
GND GND ERCAP PAVCAP IDTONE LBWSET
GND
GND
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADN2847-SPECIFICATIONS
Parameter LASER BIAS (BIAS) Output Current IBIAS Compliance Voltage IBIAS during ALS ALS Response Time CCBIAS Compliance Voltage MODULATION CURRENT (IMODP, IMODN)2 Output Current IMOD Compliance Voltage IMOD during ALS Rise Time (See Figure 4 for Typical Distribution)3 Fall Time (See Figure 5 for Typical Distribution)3 Random Jitter3 Pulsewidth Distortion3 MONITOR PD (MPD, MPD2) Current Compliance Voltage POWER SET INPUT (PSET) Capacitance Monitor Photodiode Current into RPSET Resistor Voltage EXTINCTION RATIO SET INPUT (ERSET) Allowable Resistance Range Voltage ALARM SET (ASET) Allowable Resistance Range Voltage Hysteresis CONTROL LOOP Time Constant DATA INPUTS (DATAP, DATAN, CLKP, CLKN)4 V p-p (Single-Ended, Peak-to-Peak) Input Impedance (Single-Ended) tSETUP5 (See Figure 1) tHOLD5 (See Figure 1) LOGIC INPUTS (ALS, LBWSET, CLKSEL) VIH VIL ALARM OUTPUTS (Internal 30 k Pull-Up) VOH VOL IDTONE Compliance Voltage
I OUT Ratio I IN fIN6
(VCC = 3.0 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.1 Typical values as specified at 25 C.)
Min 2 1.2 Typ Max 100 VCC 0.1 5 VCC 80 VCC 0.1 120 120 1.5 Unit mA V mA s V mA V mA ps ps ps ps A V pF A V k V k V % s s 500 50 50 100 2.4 0.8 2.4 0.8 VCC -1.5 2 0.01 100 1 0 2 VCC -1.2 1 MHz A/A A/A % V User to Supply Current Sink in the Range of 50 A to 4 mA mV ps ps V V V V V Low Loop Bandwidth Selection LBWSET = GND LBWSET = VCC Data and Clock Inputs Are AC-Coupled Conditions/Comments
IBIAS < 10% of nominal
1.2 5 1.5 80 80 1 15 50
RMS IMOD = 40 mA Average Current
1200 1.65 80 1200 1.3 25 1.3 25 1.3
50 1.1 1.2 1.1 1.2 1.1
Average Current
1.2
1.2
1.2 5 0.22 2.25
100
IBMON, IMMON, IMPDMON, IMPDMON2 IBMON, IMMON Division Ratio IMPDMON, IMPDMON2 IMPDMON to IMPDMON2 Matching Compliance Voltage
IMPD = 1200 A
-2-
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ADN2847
Parameter SUPPLY ICC7 VCC8 Min Typ 50 3.3 Max Unit mA V Conditions/Comments IBIAS = IMOD = 0
3.0
3.6
NOTES 1 Temperature range: -40C to +85C. 2 The high speed performance for the die version of ADN2847 can be achieved when using the bonding diagram shown in Figure 3. 3 Measured into a 25 W load using a 11110000 pattern at 2.5 Gbps. 4 When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin. 5 Guaranteed by design and characterization. Not production tested. 6 IDTONE may cause eye distortion. 7 ICCMIN for power calculation on page 8 is the typical I CC given. 8 All VCC pins should be shorted together. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C, unless otherwise noted.)
ORDERING GUIDE
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 V Digital Inputs (ALS, LBWSET, CLKSEL) . . -0.3 V to VCC + 0.3 V IMODN, IMODP . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 1.2 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . 150C 48-Lead LFCSP Package Power Dissipation2 . . . . . . . . . . . . . . . . (TJ max - TA)/qJA W qJA Thermal Impedance3 . . . . . . . . . . . . . . . . . . . . . 25C/W Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . 300C 32-Lead LFCSP Package Power Dissipation2 . . . . . . . . . . . . . . . . (TJ max - TA)/qJA W qJA Thermal Impedance3 . . . . . . . . . . . . . . . . . . . . . 32C/W Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Power consumption formulae are provided on page 8. 3 qJA is defined when part is soldered on a 4-layer board.
Model ADN2847ACP-32 ADN2847ACP-48 ADN2847ACP-32-RL ADN2847ACP-32-RL7 ADN2847ACP-48-RL
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
SETUP
Package Description 32-Lead LFCSP 48-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 48-Lead LFCSP
HOLD
tS
tH
DATAP/DATAN
CLKP
Figure 1. Setup and Hold Time
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN2847 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
-3-
ADN2847
2620 m
2280 m
GND2 GND2 IMMON GND3 VCC3 FAIL CLKSEL GND
IDTONE
IBMON
ALS
DEGRADE GND
DIE ROTATED 90 IN PACKAGE
GND2 VCC2 IMODN IMODN GND2 IMODP IMODP GND2 GND2 IBIAS IBIAS CCBIAS GND CLKN CLKP GND1 DATAP DATAN GND1 VCC1 GND PAVCAP ERCAP
BOTTOM
2280 m
1
LEFT TOP
2620 m
RIGHT
GND
ASET
PSET GND
IMPD
IMPDMON2
GND4 IMPD2 VCC4
LBWSET
ERSET
IMPDMON
Figure 2. Metallization Photograph
Figure 3. Bonding Diagram
DIE PAD COORDINATES*
Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Pad Name TP1 (GND) LBWSET ASET ERSET PSET TP2 (GND) IMPD IMPDMON IMPDMON2 IMPD2 GND4 VCC4 ERCAP PAVCAP TP3 (GND) VCC1 GND1 DATAN DATAP GND1 CLKP CLKN TP4 (GND) TP5 (GND) TP6 (GND) CLKSEL DEGRADE FAIL ALS
x[ m] -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -995 -925 -777 -606 -389 -200 -70 83 263 442 596 762 996 996 996 996 996 996
Y[ m] 1026 853 679 506 332 159 -15 506 -361 -534 -724 -964 -1191 -1191 -1191 -1191 -1191 -1191 -1191 -1191 -1191 -1191 -1191 -1109 -935 -762 -589 -415 -242 -4-
Pad Number 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pad Name VCC3 GND3 IMMON IBMON GND2 IDTONE GND2 GND2 VCC2 IMODN IMODN GND2 IMODP IMODP GND2 GND2 IBIAS IBIAS CCBIAS
x[ m] 996 996 996 996 996 995 995 867 713 500 396 242 88 -16 -239 -443 -633 -772 -912
Y[ m] -19 251 441 614 804 993 1133 1191 1191 1191 1191 1191 1191 1191 1191 1191 1191 1191 1191
*With the origin in the center of the die (see Figure 2).
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ADN2847
PIN CONFIGURATION 48-Lead LFCSP 32-Lead LFCSP
32 CCBIAS 31 IBIAS 30 GND2 29 GND2 28 IMODP 27 GND2 26 IMODN 25 VCC2
48 CCBIAS 47 IBIAS 46 IBIAS 45 GND2 44 GND2 43 IMODP 42 IMODP 41 GND2 40 IMODN 39 IMODN 38 VCC2 37 GND2
ERCAP 13 PAVCAP 14 TP3 15 VCC1 16 GND1 17 DATAN 18 DATAP 19 GND1 20 CLKP 21 CLKN 22 TP4 23 TP5 24
PIN FUNCTION DESCRIPTIONS
Pin Number 48-Lead 32-Lead 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 REV. 0 1 2 3 4 5 6
Mnemonic TP1 LBWSET ASET ERSET PSET TP2 IMPD IMPDMON IMPDMON2 IMPD2 GND4 VCC4 ERCAP PAVCAP TP3 VCC1 GND1 DATAN DATAP GND1 CLKP CLKN TP4 TP5 TP6 CLKSEL DEGRADE FAIL ALS VCC3 GND3 IMMON IBMON
Function Test Pin. In normal operation, TP1 = GND. Select Low Loop Bandwidth Alarm Current Threshold Setting Pin Extinction Ratio Set Pin Average Optical Power Set Pin Test Pin. In normal operation, TP2 = GND. Monitor Photodiode Input Mirrored Current from Monitor Photodiode Mirrored Current from Monitor Photodiode2 (for Use with Two MPDs) Monitor Photodiode Input 2 (for Use with Two MPDs) Supply Ground Supply Voltage Extinction Ratio Loop Capacitor Average Power Loop Capacitor Test Pin. In normal operation, TP3 = GND. Supply Voltage Supply Ground Data, Negative Differential Terminal Data, Positive Differential Terminal Supply Ground Data Clock Positive Differential Terminal, Used if CLKSEL = VCC Data Clock Negative Differential Terminal, Used if CLKSEL = VCC Test Pin. In normal operation, TP4 = GND. Test Pin. In normal operation, TP5 = GND. Test Pin. In normal operation, TP6 = GND. Clock Select (Active = VCC), Used if Data Is Clocked into Chip DEGRADE Alarm Output FAIL Alarm Output Automatic Laser Shutdown Supply Voltage Supply Ground Modulation Current Mirror Output Bias Current Mirror Output -5-
7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
ERCAP 9 PAVCAP 10 VCC1 11 DATAN 12 DATAP 13 GND1 14 CLKP 15 CLKN 16
TP1 1 LBWSET 2 ASET 3 ERSET 4 PSET 5 TP2 6 IMPD 7 IMPDMON 8 IMPDMON2 9 IMPD2 10 GND4 11 VCC4 12
PIN 1 INDICATOR
ADN2847
TOP VIEW
36 GND2 35 IDTONE 34 GND2 33 IBMON 32 IMMON 31 GND3 30 VCC3 29 ALS 28 FAIL 27 DEGRADE 26 CLKSEL 25 TP6
LBWSET 1 ASET 2 ERSET 3 PSET 4 IMPD 5 IMPDMON 6 GND4 7 VCC4 8
PIN 1 INDICATOR
ADN2847
TOP VIEW
24 IBMON 23 IMMON 22 GND3 21 VCC3 20 ALS 19 FAIL 18 DEGRADE 17 CLKSEL
ADN2847
PIN FUNCTION DESCRIPTIONS (continued)
Pin Number 48-Lead 32-Lead 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
40
Mnemonic GND2 IDTONE GND2 GND2 VCC2 IMODN IMODN GND2 IMODP IMODP GND2 GND2 IBIAS IBIAS CCBIAS
Function Supply Ground IDTONE (Requires External Current Sink to Ground) Supply Ground Supply Ground Supply Voltage Modulation Current Negative Output. Connect via a matching resistor to VCC. Modulation Current Negative Output. Connect via a matching resistor to VCC. Supply Ground Modulation Current Positive Output. Connect to laser diode. Modulation Current Positive Output. Connect to laser diode. Supply Ground Supply Ground Laser Diode Bias Current Laser Diode Bias Current Extra Laser Diode Bias when AC-Coupled Current Sink
GENERAL
25 26 26 27 28 28 29 30 31 31 32
30
Laser diodes have current-in to light-out transfer functions as shown in Figure 6. Two key characteristics of this transfer function are the threshold current, ITH, and slope in the linear region beyond the threshold current, referred to as slope efficiency, LI.
ER = P1 P0
COUNT - %
20 OPTICAL POWER
P1
PAV =
P1 + P0 2
10
P PAV I P0 ITH CURRENT LI = P I
0 76
78
80
82
84
86 88 90 92 RISE TIME - ps
94
96
98
100
Figure 4. Rise Time Distribution Under WorstCase Operating Conditions
Control
40
Figure 6. Laser Transfer Function
30
A monitor photodiode, MPD, is required to control the LD. The MPD current is fed into the ADN2847 to control the power and extinction ratio, continuously adjusting the bias current and modulation current in response to the laser's changing threshold current and light-to-current slope efficiency. The ADN2847 uses automatic power control, APC, to maintain a constant average power over time and temperature. The ADN2847 uses closed-loop extinction ratio control to allow optimum setting of extinction ratio for every device. Thus SONET/SDH interface standards can be met over device variation, temperature, and laser aging. Closed-loop modulation control eliminates the need to either overmodulate the LD or include external components for temperature compensation. This reduces research and development time and second sourcing issues caused by characterizing LDs. Average power and extinction ratio are set using the PSET and ERSET pins, respectively. Potentiometers are connected between these pins and ground. The potentiometer RPSET is used to change the average power. The potentiometer RERSET is used to adjust the extinction ratio. Both PSET and ERSET are kept 1.2 V above GND. -6- REV. 0
COUNT - %
20
10
0 80
82
84
86
88
90 92 94 96 FALL TIME - ps
98
100 102 104
Figure 5. Fall Time Distribution Under WorstCase Operating Conditions
ADN2847
The RPSET and RERSET potentiometers can be calculated using the following formulas. 1.2 V R PSET = ( ) I AV
RERSET = 1.2V () ER - 1 x x PAV ER + 1
The laser degrade alarm, DEGRADE, is provided to give a warning of imminent laser failure if the laser diode degrades further or environmental conditions continue to stress the LD, such as increasing temperature. The laser fail alarm, FAIL, is activated when the transmitter can no longer be guaranteed to be SONET/SDH compliant. This occurs when one of the following conditions arises:
* *
I MPD _ CW PCW
The ASET threshold is reached. The ALS pin is set high. This shuts off the modulation and bias currents to the LD, resulting in the MPD current dropping to zero. This gives closed-loop feedback to the system that ALS has been enabled.
where: IAV is the average MPD current. PCW is the dc optical power specified on the laser data sheet. IMPD_CW is the MPD current at that specified PCW. PAV is the average power required. ER is the desired extinction ratio (ER = P1/P0). Note that IERSET and IPSET will change from device to device; however, the control loops will determine actual values. It is not required to know exact values for LI or MPD optical coupling.
Loop Bandwidth Selection
DEGRADE will be raised only when the bias current exceeds 90% of ASET current.
Monitor Currents
For continuous operation, the user should hardwire the LBWSET pin high and use 1 F capacitors to set the actual loop bandwidth. These capacitors are placed between the PAVCAP and ERCAP pins and ground. It is important that these capacitors are low leakage multilayer ceramics with an insulation resistance greater than 100 G or a time constant of 1000 sec, whichever is less. Operation Mode Continuous 50 Mbps to 3.3 Gbps Optimized for 2.5 Gbps to 3.3 Gbps Recommended Recommended LBWSET PAVCAP ERCAP High 1 F 1 F
IBMON, IMMON, IMPDMON, and IMPDMON2 are current controlled current sources from VCC. They mirror the bias, modulation, and MPD current for increased monitoring functionality. An external resistor to GND gives a voltage proportional to the current monitored. If the monitoring functions IMPDMON and IMPDMON2 are not required, the IMPD and IMPD2 pins must be grounded and the monitor photodiode output must be connected directly to the PSET pin.
Dual MPD DWDM Function (48-Lead LFCSP Only)
Low
22 nF
22 nF
The ADN2847 has circuitry for a second monitor photodiode, MPD2. The second photodiode current is mirrored to IMPDMON2 for wavelength control purposes and is summed internally with the first monitor photodiode current for the power control loop. For single MPD circuits, the MPD2 pin is tied to GND. This enables the system designer to use the two currents to control the wavelength of the laser diode using various optical filtering techniques inside the laser module. If the monitor current functions IMPDMON and IMPDMON2 are not required, then the IMPD and IMPD2 pins can be grounded and the monitor photodiode output can be connected directly to PSET.
IDTONE (48-Lead LFCSP Only)
Setting LBSET low and using 22 nF capacitors results in a shorter loop time constant (a 10x reduction over using 1 F capacitors and keeping LBWSET high.)
Alarms
The ADN2847 is designed to allow interface compliance to ITUT-G958 (11/94) section 10.3.1.1.2 (transmitter fail) and section 10.3.1.1.3 (transmitter degrade). The ADN2847 has two active high alarms, DEGRADE and FAIL. A resistor between ground and the ASET pin is used to set the current at which these alarms are raised. The current through the ASET resistor is a ratio of 100:1 to the FAIL alarm threshold. The DEGRADE alarm will be raised at 90% of this level. Example:
The IDTONE pin is supplied for fiber identification/supervisory channels or control purposes in WDM. This pin modulates the optical one level over a possible range of 2% of minimum IMOD to 10% of maximum IMOD. The level of modulation is set by connecting an external current sink between the IDTONE pin and ground. There is a gain of two from this pin to the IMOD current. Figure 9 shows how an AD9850/AD9851 or the AD9834 may be used with the ADN2847 to allow fiber identification. If the ID_TONE function is not used, the IDTONE pin should be tied to VCC. Note that using IDTONE during transmission may cause optical eye degradation.
Data, Clock Inputs
I FAIL = 50 mA so I DEGRADE = 45 mA
I ASET
*R
I 50 mA = FAIL = = 500 A 100 100
= 1.2V 1.2 = = 2.4 k I ASET 500 A
ASET
* The smallest valid value for R ASET is 1.2 k, since this corresponds to the I BIAS maximum of 100 mA.
Data and clock inputs are ac-coupled (10 nF capacitors are recommended) and terminated via a 100 internal resistor between DATAP and DATAN, and also between the CLKP and CLKN pins. There is a high impedance circuit to set the common-mode voltage that is designed to allow for maximum input voltage
REV. 0
-7-
ADN2847
headroom over temperature. It is necessary that ac coupling is used to eliminate the need for matching between commonmode voltages.
ADN2847
DATAP (TO FLIP-FLOPS) DATAN 50 50 VREG R R = 2.5k , DATA R = 3k , CLK
currents are turned off. Correct operation of ALS can be confirmed by the FAIL alarm being raised when ALS is asserted. Note that this is the only time DEGRADE will be low while FAIL is high.
Alarm Interfaces
The FAIL and DEGRADE outputs have an internal pull-up resistor of 30 k used to pull the digital high value to VCC. However, the alarm can be overdriven with an external resistor allowing alarm interfacing to non-VCC levels. Non-VCC alarm output levels must be below the VCC used for the ADN2847.
Power Consumption
400 A TYP
The ADN2847 die temperature must be kept below 125oC. Both LFCSP packages have an exposed paddle, which should be connected in such a manner that is is at the same potential as the ADN2847 ground pins. The JA for both packages is shown in the Absolute Maximum Ratings. Power consumption can be calculated using
Figure 7. AC Coupling of Data Inputs
I CC = I CCMIN + 0.3 I MOD
For input signals that exceed 500 mV p-p single ended, it is necessary to insert an attenuation circuit as shown in Figure 8.
ADN2847
RIN DATAN/CLKN NOTE THAT RIN = 100 = THE DIFFERENTIAL INPUT IMPEDANCE OF THE ADN2847
P = VCC x I CC + I BIAS x VBIAS _ PIN + I MOD VMODP _ PIN + VMODN _ PIN / 2
(
)
(
)
T DIE = T AMBIENT + JA x P
Thus, the maximum combination of IBIAS + IMOD must be calculated. Where: ICCMIN = 50 mA, the typical value of ICC provided on page 3 with IBIAS = IMOD = 0 TDIE = die temperature TAMBIENT = ambient temperature VBIAS_PIN = voltage at IBIAS pin VMODP_PIN = average voltage at IMODP pin VMODN_PIN = average voltage at IMODN pin
Laser Diode Interfacing
R1 R3 R2
DATAP/CLKP
Figure 8. Attenuation Circuit
CCBIAS
When the laser is used in ac-coupled mode, the CCBIAS and IBIAS pins should be tied together (Figure 12). In dc-coupled mode, CCBIAS should be tied to VCC.
Automatic Laser Shutdown
The ADN2847 ALS allows compliance to ITU-T-G958 (11/94), section 9.7. When ALS is logic high, both bias and modulation
Many laser diodes designed for 2.5 Gbs operation are packaged with an internal resistor to bring the effective impedance up to 25 in order to minimize transmission line effects. In high current applications, the voltage drop across this resistor combined with the laser diode forward voltage makes direct connection between the laser and the driver impractical in a 3 V system. AC coupling the driver to the laser diode removes this headroom constraint.
REF CLOCK 20MHz-180MHz 10kHz-1MHz CLKIN 1/2
9 35
1.25mA-20mA
21
AD8602
LP FILTER (DC-COUPLED)
IDTONE
0.125mA-2mA BC550
AD9850/AD9851 AD9834
DDS
12 20
IOUT
50
ADN2847
500 1/2
IOUT 50 37.5 A-600 A
RSET
CONTROLLER BC550
AD8602
50 A-800 A
32
1000
IMMON
1300
Figure 9. Application Curcuit to Allow Fiber Identification Using the AD9850/AD9851
-8-
REV. 0
ADN2847
Caution must be taken when choosing component values for ac coupling to ensure that the time constants (L/R and RC, see Figure 12) are sufficiently long for the data rate and expected number of CIDs (consecutive identical digits). Failure to do this could lead to pattern dependent jitter and vertical eye closure. For designs with low series resistance, or where external components become impractical, the ADN2847 supports direct connection to the laser diode (see Figure 11). In this case, care must be taken to ensure that the voltage drop across the laser diode does not violate the minimum compliance voltage on the IMODP pin.
Optical Supervisor
TX RX CLK CS SDI SDO CLK CS DATAP DATAN IDTONE DAC1 DAC2 PSET ERSET
DATAN DATAP
VCC
VCC
IMPD
VCC
ADN2847
ADN2850
IMODP IBIAS
IDTONE
The PSET and ERSET potentiometers may be replaced with a dual-digital potentiometer, the ADN2850 (see Figure 10). The ADN2850 provides an accurate digital control for the average optical power and extinction ratio and ensures excellent stability over temperature.
Figure 10. Application Using the ADN2850 a Dual 10-Bit Digital Potentiometer with an Extremely Low Temperature Coefficient as an Optical Supervisor
ALS
FAIL DEGRADE
1k VCC 1.5k 36 1.5k 25
IDTONE
IBMON
DEGRADE
IMMON
GND2
GND2
GND3
37
CLKSEL
VCC3
GND
ALS
FAIL
GND2 VCC2
GND GND CLKN CLKP GND1
24
GND
VCC VCC
*
IMODN IMODN
10nF 10nF
CLKN CLKP
MPD
LD *
GND2 IMODP * * GND2 GND2 IBIAS 10 H VCC 48 IMODP
ADN2847
DATAP DATAN GND1 VCC1 GND 22nF 22nF
10nF 10nF
DATAP DATAN
ERSET
CCBIAS
IMPDMON2
IBIAS
PAVCAP
IMPDMON
LBWSET
IMPD2
ERCAP
GND4
ASET
PSET
IMPD
GND
GND
VCC4
13
1 ** ** 1.5k
12
VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2847 AND THE LASER DIODE USED. CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF CAPACITORS IN PARALLEL WITH 10nF CAPACITORS.
VCC LD = LASER DIODE MPD = MONITOR PHOTODIODE 100nF 100nF 100nF 100nF 10 F
GND NOTES * DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED. ** FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
Figure 11. DC-Coupled 3.3 Gbps Test Circuit, Data Not Clocked
REV. 0
-9-
ADN2847
ALS FAIL DEGRADE
1k VCC * * * * * 36 VCC 1.5k 1.5k 25
IDTONE
IBMON
GND2
IMMON
DEGRADE
GND2
GND3
37 * VCC
CLKSEL
VCC3
GND
ALS
FAIL
GND2 VCC2 IMODN IMODN
GND GND CLKN CLKP GND1
24
GND
10nF 10nF
CLKN CLKP
MPD
LD * * * *
GND2 IMODP IMODP GND2 GND2 IBIAS 1H 48
ADN2847
DATAP DATAN GND1 VCC1 GND 1F 1F
10nF 10nF
DATAP DATAN
ERSET
CCBIAS
IMPDMON2
IBIAS
PAVCAP
IMPDMON
LBWSET
IMPD2
ERCAP
GND4
ASET
PSET
IMPD
GND
GND
VCC4
13
1 ** ** 1.5k
12
VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2847 AND THE LASER DIODE USED. CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF CAPACITORS IN PARALLEL WITH 10nF CAPACITORS.
VCC LD = LASER DIODE MPD = MONITOR PHOTODIODE 100nF 100nF 100nF 100nF 10 F
GND NOTES * DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED **FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
Figure 12. AC-Coupled 50 Mbps to 3.3 Gbps Test Circuit, Data Not Clocked
Figure 13. A 2.5 Gbps Optical Eye at 25C. Average Power = 0 dBm, Extinction Ratio = 10 dB, PRBS 31 Pattern. Eye Obtained Using a DFB Laser.
Figure 14. A 2.5 Gbps Optical Eye at 85C. Average Power = 0 dBm, Extinction Ratio = 10 dB, PRBS 31 Pattern. Eye Obtained Using a DFB Laser.
-10-
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ADN2847
OUTLINE DIMENSIONS 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)
Dimensions shown in millimeters
0.30 0.23 0.18
48 1
7.00 BSC SQ
0.60 MAX 0.60 MAX
37 36
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
BOTTOM VIEW
5.25 4.70 2.25
0.50 0.40 0.30 0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COPLANARITY 0.08
25 24
12 13
1.00 0.90 0.80 0.25 REF
5.50 REF
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
32-Lead Frame Chip Scale Package [LFCSP] (CP-32)
Dimensions shown in millimeters
5.00 BSC SQ
0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
4.75 BSC SQ
0.50 BSC
BOTTOM VIEW
3.25 3.10 SQ 2.95
8
0.50 0.40 0.30 12 MAX 0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 REF COPLANARITY 0.08
17 16
9
3.50 REF
1.00 0.90 0.80 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
REV. 0
-11-
-12-
C02745-0-1/03(0)
PRINTED IN U.S.A.

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